 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Features Functional Description The CY2310ANZ is a 3.3V buffer designed to distribute high speed clocks in mobile PC applications. The part has 10 outputs, eight of which are used to drive up to four SDRAM SO-DIMMs. The remaining are used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II(R) processors. The CY2310ANZ can be used in conjunction with the CY2281 or similar clock synthesizer for a full Pentium II motherboard solution. The CY2310ANZ also includes a serial interface which can enable or disable each output clock. During power up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. One input to 10 output buffer and driver Supports up to four SDRAM SO-DIMMs Two additional outputs for feedback Serial interface for output control Low skew outputs Up to 100 MHz operation Multiple VDD and VSS pins for noise reduction Dedicated OE pin for testing Space saving 28-pin SSOP package 3.3V operation Logic Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 Serial Interface Decoding SCLOCK SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDATA OE Cypress Semiconductor Corporation Document #: 38-07142 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 12, 2009 [+] Feedback CY2310ANZ Pin Configuration Figure 1. Pin Diagram: 28-Pin SSOP Top View VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM8 VSS VDDIIC SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD SDRAM7 SDRAM6 VSS VDD SDRAM5 SDRAM4 VSS OE VDD SDRAM9 VSS VSSIIC SCLOCK Table 1. Pin Summary Name VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0-3] SDRAM [4-7] SDRAM [8-9] Pins 1, 5, 10, 19, 24, 28 4, 8, 12, 17, 21, 25 13 16 9 20 14 15 2, 3, 6, 7 22, 23, 26, 27 11, 18 Description 3.3V Digital voltage supply Ground Serial interface voltage supply Ground for serial interface Input clock Output Enable, three-states outputs when LOW. Internal pull up to VDD Serial data input, internal pull-up to VDD Serial clock input, internal pull-up to VDD SDRAM byte 0 clock outputs SDRAM byte 1 clock outputs SDRAM byte 2 clock outputs Document #: 38-07142 Rev. *C Page 2 of 9 [+] Feedback CY2310ANZ Device Functionality OE 0 1 SDRAM [0-17] High-Z 1 x BUF_IN Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin No. 27 26 23 22 ----Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Initialize to 0 Initialize to 0 Initialize to 0 Initialize to 0 Serial Configuration Map The serial bits are read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Reserved and unused bits should be programmed to "0". Serial interface address for the CY2310ANZ is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin No. 18 11 ------Description SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin No. ----7 6 3 2 Initialize to 0 Initialize to 0 Initialize to 0 Initialize to 0 SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Description Document #: 38-07142 Rev. *C Page 3 of 9 [+] Feedback CY2310ANZ Maximum Ratings Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage (Except BUF_IN) ....... -0.5V to VDD + 0.5V DC Input Voltage (BUF_IN) ............................-0.5V to +7.0V Storage Temperature ................................. -65C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min 3.135 0 20 Max 3.465 70 30 7 50 Unit V C pF pF ms Electrical Characteristics Parameter VIL VILiic VIH IIL IIL IIH VOL VOH IDD IDD IDD IDD IDDS . Description Input LOW Voltage[1] Input LOW Voltage Input HIGH Voltage[1] VIN = 0V VIN = 0V VIN = VDD IOL = 25 mA IOH = -36 mA Unloaded outputs, 100-MHz Loaded outputs, 100-MHz Unloaded outputs, 66.67-MHz Loaded outputs, 66.67-MHz BUF_IN=VDD or VSS All other inputs at VDD 2.4 200 360 150 230 500 -10 Input LOW Current (BUF_IN input) Input LOW Current (Except BUF_IN Pin) Input HIGH Current Output LOW Output HIGH Voltage[2] Voltage[2] Test Conditions Except serial interface pins For serial interface pins only 2.0 -10 10 100 10 0.4 Min Max 0.8 0.7 Unit V V V A A A V V mA mA mA mA A Supply Current[2] Supply Current Supply Current[2] Supply Current Supply Current Notes 1. BUF_IN input has a threshold voltage of VDD/2. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Document #: 38-07142 Rev. *C Page 4 of 9 [+] Feedback CY2310ANZ Switching Characteristics[3] Parameter Name Maximum Operating Frequency Duty Cycle[2, 4] = t2 / t1 t3 t4 t5 t6 t7 t8 t9 Rising Edge Rate [2] [2] [2] Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V All outputs equally loaded Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Min 45.0 0.9 0.9 1.0 1.0 1.0 1.0 Typ 50.0 1.5 1.5 150 3.5 3.5 5 20 Max 100 55.0 4.0 4.0 250 5.0 5.0 12 30 Unit MHz % V/ns V/ns ps ns ns ns ns Falling Edge Rate Output to Output Skew SDRAM Buffer LH Prop. Delay[2] SDRAM Buffer HL Prop. Delay[2] SDRAM Buffer Enable Delay [2] [2] SDRAM Buffer Disable Delay Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V Figure 3. All Outputs Rise/Fall Time 2.4V 0.4V t3 2.4V 0.4V t4 3.3V 0V OUTPUT Figure 4. Output-Output Skew 1.5V OUTPUT OUTPUT t5 1.5V Notes 3. All parameters specified with loaded outputs. 4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/n Document #: 38-07142 Rev. *C Page 5 of 9 [+] Feedback CY2310ANZ Figure 5. SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 Figure 6. SDRAM Buffer Enable and Disable Times OE Three-State OUTPUTS t8 Active t9 Figure 7. Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD GND Document #: 38-07142 Rev. *C Page 6 of 9 [+] Feedback CY2310ANZ Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Summary Surface mount, low ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. If a Ferrite Bead is used, a 10 F to 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Document #: 38-07142 Rev. *C Page 7 of 9 [+] Feedback CY2310ANZ Ordering Information Ordering Code CY2310ANZPVC-1T Pb-Free CY2310ANZPVXC-1 CY2310ANZPVXC-1T 28-Pin SSOP 28-Pin SSOP - Tape and Reel Commercial Commercial Package Type 28-Pin SSOP - Tape and Reel Operating Range Commercial Package Diagram Figure 8. 28-Pin (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Document #: 38-07142 Rev. *C Page 8 of 9 [+] Feedback CY2310ANZ Document History Page Document Title: CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Document Number: 38-07142 Rev. ** *A *B *C ECN No. 110251 121829 310555 2635282 Orig. of Change DSG RBI RGL KVM/PYRS Submission Datee 11/18/01 12/14/02 See ECN 01/13/09 Description of Change Change from Spec number: 38-00659 to 38-07142 Power up requirements added to Operating Conditions Information Added Lead-free Devices Remove CY2310ANZPVC-1 from Ordering Information table Replace "Lead-Free" with "Pb-Free" Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/ (c) Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07142 Rev. *C Revised January 12, 2009 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
Price & Availability of CY2310ANZ09
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |